Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called “erase blocks”. The memory cells of a Flash memory array are typically arranged into a “NOR” architecture (each cell directly coupled to a bitline) or a “NAND” architecture (cells coupled into “strings” of cells, such that each cell is coupled indirectly to a bitline and requires activating the other cells of the string for access). Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
FIG. 1 shows a simplified diagram of a Flash memory subsystem 134 of the prior art. In the Flash memory subsystem 134, a Flash memory controller 130 is coupled 132 to one or more Flash memory devices 100. The Flash memory controller 130 contains a control state machine 110 that directs the operation of the Flash memory device(s) 100; managing the Flash memory array 112 and updating internal RAM control registers and tables 114 and the non-volatile erase block management registers and tables 128. The RAM control registers and tables 114 are loaded at power up from the non-volatile erase block management registers and tables 128 by the control state machine 110. The Flash memory array 112 of each Flash memory device 100 contains a sequence of erase blocks 116. Each erase block 116 contains a series of sectors 118 that are typically each written to a single row of the memory array 112 and include a user data space or area 120 and an associated control or overhead data space or area 122. The control/overhead data space 122 contains overhead information for operation of the sector it is associated with. Such overhead information typically includes, but is not limited to, erase block management (EBM) data, sector status information, or an error correction code (ECC, not shown). ECC's allow the Flash memory 100 and/or the Flash memory controller 130 to detect data errors in the user data space 120 and attempt to recover the user data if possible.
The user data space 120 in each sector 118 is typically one or more multiples of 512 bytes long (depending on memory array 112 row size), wherein one or more logical operating system (OS) sectors of 512 bytes each or multiple logically addressed data words can be stored on the row or sector 118. In a typical Flash memory device 100 each erase block 116 typically contains 16 or more physical sectors 118. Each new 512 bytes of user data and its associated overhead data are together written into an available erase block sector 118 (i.e., User data A with Overhead data A within a single erase block sector 118) as the user data arrives at the Flash memory 100. User data is typically written sequentially into the sectors 118 of an erase block 116 until it is filled. It is noted that other configurations of Flash memory subsystems 134, having Flash memory devices 100 and Flash memory controllers 130, are well known in the art, including such devices that integrate the functions of the separate Flash memory controller and Flash memory device into a single device.
A problem with Flash memories is that each erase block sector 118 stores the user data and the overhead information, which includes the error correction codes, within close proximity to each other or, alternatively, on the same physical row of the memory array 112. Because of this, an error in one or more sectors 118 of an erase block 116 of the Flash memory 100 due to physical damage, impurity migration, write fatigue, electrical transients, or another reason can also affect the overhead data associated with those sectors. This increases the likelihood of a loss of data (if the ECC is damaged also) or even the loss of the ability to access the affected sector occurring (if the sector management data is damaged) when such an error happens.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a Flash memory device or Flash memory handing routine that has a fault tolerant erase block sector architecture and data/overhead information storage method.